Cadence SP&R Upgrade Speeds Design of Large Chips

Broad New Release of Synthesis/Place-and-Route Design Technology Accelerates Timing and Signal Integrity Closure for SoC Encounter Flow

SAN JOSE, Calif.--(BUSINESS WIRE)--May 20, 2002-- Cadence Design Systems, Inc. (NYSE:CDN - News), the world's leading supplier of electronic design products and services, today introduced a broad upgrade to its SP&R (synthesis/place-and-route) integrated RTL-to-GDSII design solution that enables designers to produce higher-performance chips in shorter design cycles than ever before. The new Cadence® SP&R technology delivers significantly more powerful timing and signal integrity optimization, more than twice the performance in synthesis and routing, and next-generation power planning for large, complex integrated circuits (ICs).

This release of Cadence SP&R technology includes enhancements to BuildGates® synthesis, Physically Knowledgeable Synthesis (PKS), Silicon Ensemble®, and SoC Encounter place-and-route systems which shorten the time it takes to design multi-million-gate digital ICs.

Cadence SP&R Enhancements Address Deep Sub-Micron Challenges

Cadence SP&R has enhanced performance and features to address the design challenges of sub-0.13-micron process technology:

• Physical synthesis and routing performance improvements -- Delivers an average of two times the speed in physical synthesis and advanced high-level optimizations for superior quality of results. New multiple-CPU capability speeds up core Silicon Ensemble routing performance as much as 10 times, and complements multi-CPU capability in NanoRoute.
• Flexible and productive next-generation power planner -- Provides innovative features enabling maximized flexibility and productivity in power planning and power routing.
• Post-route signal integrity optimization -- Tightly integrates signal integrity prevention, advanced crosstalk analysis -- such as noise-on-delay and glitch analysis -- with CeltIC technology and timing-driven post-route repair for better quality of results. The embedded common engines used during all phases of signal integrity analysis, prevention, and correction help ensure rapid signal integrity closure and reduces multiple iterations for faster time-to-market.

Other enhanced features include:

• Physically knowledgeable power analysis and optimization -- Concurrently optimizes designs for timing and power consumption using physical information. The integration of power optimization in physical synthesis delivers early predictability for power consumption and 20 to 60 percent power reduction. This is critical for chip designers targeting power-sensitive applications, such as handheld consumer products and satellite systems. The physically knowledgeable, low-power synthesis supports comprehensive RTL optimizations, such as clock-gating, its integration with clock-tree synthesis, and sleep mode, as well as gate-level optimizations. Concurrent optimization ensures that the power reduction is achieved without affecting the timing performance.
• Advanced datapath optimization integrated in logic and physical synthesis -- Enables concurrent optimization of advanced datapath and control logic in a single synthesis solution. This allows engineers to describe complex datapath design along with surrounding control logic using simple extensions to Verilog 2001 and VHDL. The result is high performance datapath and control logic without the problems of multiple flows and manual intervention. In addition, the datapath and control are optimized in the same timing context, eliminating multiple iterations.
• Introducing BuildGates Extreme synthesis -- Delivering high performance synthesis, multi-million-gate capacity, more than two times faster turnaround time, and integrated low-power and advanced datapath optimization to satisfy advanced design performance needs.
• Routing enhancements satisfy requirements for sub-0.13-micron process technology -- Provides designers with a multitude of automated features to handle requirements now mandated by foundries for leading-edge designs. These include complex wide-wire spacing rules, minimum area rules, double-cut via requirements for signal wires and pins, advanced hierarchical process antenna rules, new requirements for copper process technologies, metal density checking and fill, and metal slotting/splitting.

"With this new release of our SP&R technology, Cadence is advancing the bar for IC design and implementation at 0.13-micron and below technology," said Eric Filseth, vice president of SP&R marketing at Cadence. "The integrated signal integrity prevention, analysis and repair, and performance enhancements in synthesis and routing deliver a superior design flow to our customers."

Pricing and Availability

The new release of Cadence SP&R is available immediately for Sun Solaris and HP's HP-UX UNIX operating systems. One-year U.S. list prices for BuildGates synthesis, BuildGates Extreme synthesis, and PKS physical synthesis products start at $20,000, $50,000, and $150,000 respectively. U.S. list prices for Silicon Ensemble and SoC Encounter start at $400,000 and $695,000. For information on international pricing or about upgrade paths for current customers, please contact a local Cadence office.

About Cadence

Cadence is the largest supplier of electronic design technologies, methodology services, and design services. Cadence solutions are used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 5,600 employees and 2001 revenues of approximately $1.4 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services are available at www.cadence.com.

Note to Editors: Cadence, the Cadence logo, BuildGates, and Silicon Ensemble are registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

    Cadence SP&R Upgrade Speeds Design of Large Chips
    Addendum

HERE'S WHAT ELECTRONICS INDUSTRY LEADERS ARE SAYING

ABOUT THE NEW CADENCE SP&R:

Bill Young, senior CAD engineer for Agilent Technologies

"As an early adopter of next generation process technologies, Agilent is always pushing the envelope when it comes to chip size, performance and complexity. We need solutions that can quickly handle timing and design closure while natively addressing new design and manufacturing requirements for advanced processes. The latest Cadence Silicon Ensemble release, with its new power planner, integrated signal integrity capabilities, and its handling of our new process rules automatically on-the-fly, gives us the necessary features and functionality to continue to deliver the leading-edge technologies that our customers demand."

Tsunesato Munakata, VP of Design Engineering Center-West, Mitsubishi Electric & Electronics USA, Inc.

"We have extensively used Cadence SP&R to deliver timing closure on leading edge designs at 500 MHz and beyond. The new release of PKS has demonstrated reduced iterations on very challenging designs. With integration of PKS in our 0.13-micron ASIC design flow, our customers will benefit from the enhanced timing closure and rapid time to market."

David Gross, Wireless Methodology Manager, Motorola, Inc.

"In managing the Wireless team that evaluated the latest release of SP&R I will definitely leverage key features of this solution in our upcoming design activities. With the addition of multi-CPU routing and metal density checking and filling features in this release, Cadence has shown considerable foresight and forward-thinking to help us handle the ever-increasing complexity and size of our designs. Specifically, multi-CPU routing has reduced our routing times in a dramatic fashion while the metal density checking and fill capability allows us to simply meet our requirements for deeper-submicron process rules."

Jamshed Qamar, vice president of ASIC Business Development, Oki Semiconductor

"We, at Oki Semiconductor, pride ourselves on providing predictable design closure and rapid turnaround time for our ASIC customers. The powerful timing optimization and tight correlation to final implementation delivered by PKS has been critical to our success with several leading-edge customers. The latest release of PKS represents faster design cycle time over our previous ASIC flow and as a result, we've integrated this new release into our flow. Our customers will greatly benefit from the faster turnaround time of PKS."

Ching-Hsiang Yang, CAD manager of Sunplus Technology Co., Ltd.

"Fast time-to-market is essential for our consumer electronic applications and PKS physical synthesis has consistently delivered the necessary rapid timing closure for us. In the past 12 months, we have taped out 10 chips with Cadence SP&R. With the latest release of PKS, we have seen over two times runtime speedup and better timing for several designs. This superior quality-of-results and excellent turnaround-time will enable us to deliver our high-performance chipsets even faster."

Masami Murakata, senior manager, EDA Technology Department at Toshiba Microelectronics Corporation

"Timing closure and design closure are serious problems that are exacerbated by poor predictability and disjointed tool flows. The robust SP&R technology engines deliver tight correlation throughout our design flow and enable us to rapidly and confidently predict and achieve timing closure from RTL to GDSII. We are also impressed with the integrated CeltIC signal integrity features of this release. By using CeltIC we expect we can dramatically reduce time for resolving false violations which improves our design cycle time and turn-around-time."

     Cadence Design Systems, Inc., San Jose
     Parvesh Bal-Sandhu, 408/894-2512
     parvesh@cadence.com
      or
     Armstrong Kendall, Inc.
     Matt McGinnis, 503/672-4689